1. Field of the Invention
The present invention relates to a circuit, and more particularly, to a frequency divider circuit.
2. Description of the Related Art
When designing a circuit, there is usually a need for clock signals of periods different from that of the main clock signal. Power supporting circuits, for example, usually require clock signals of different periods for different channels of power outputs such that the total amount of power output is more uniformly distributed over time. However, it is not efficient to design corresponding clock generating circuits for every clock signal of a different period. Therefore, there is a need for a frequency divider circuit which divides the frequency of a clock signal to generate clock signals of different periods. The ratios of the periods of clock signals generated by an ordinary frequency divider circuit to the period of the original clock signal are usually exponents of 2, such as 2, 4 or 8. The applications of ordinary frequency divider circuits are thus limited.
U.S. Pat. No. 4,348,640 discloses a frequency divider circuit comprising three JK flip-flops and five logic gates, wherein the frequency divider circuit down-converts a clock signal into another signal with a period three times of the period of the original clock signal. However, the frequency divider circuit requires a lot of flip-flops and logic gates, and also requires a lot of effort to be adapted to generate signals of different periods.
U.S. Pat. No. 6,389,095 discloses a frequency divider circuit comprising two D flip-flops, an OR gate and a NOR gate, wherein the frequency divider circuit down-converts a clock signal into another signal with a period three times of the period of the original clock signal. Even though the frequency divider circuit reduces the number of the required transistors, it still requires an OR gate and a NOR gate. In CMOS manufacturing process, the frequency divider circuit requires at least 10 transistors, which does not meet the requirement for cost efficiency. In addition, the frequency divider circuit requires a lot of effort to be adapted to generate signals of different periods, and hence its usage is limited.
Accordingly, there is a need to design a frequency divider circuit with simple structure that can be easily adapted to generate signals of different periods to meet the requirement of modern circuit design.